View BT261_775993.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
The BT261 HSYNC Line Lock Controller is designed specifically for image capture applications. Either composite video or TTL composite sync information is input via VIDEO. An internal sync separator separates horizontal and vertical sync information. Programmable horizontal and vertical video timing enables recovery of both standard and nonstandard timing information. An external VCO may be used in conjunction with the on-chip phase comparator for implementation of clocks locked to the horizontal frequency. Alternately, a high-speed clock (OSC) may be divided down to generate the pixel clock. The phase of the generated pixel clock is adjusted to align with the noise-gated CSYNC. The higher the OSC clock rate, the lower the pixel clock jitter (the maximum being one half the OSC clock period). The OSC inputs may be configured to be either TTL or ECL compatible. Thus, four TTL clocks, two TTL clocks and one differential ECL clock, or two differential ECL clocks may be used. The ECL clock inputs are designed to be driven by 10KH ECL using a single +5 V supply. The CLAMP and ZERO outputs are programmed by the MPU to DC restore the video signal and to zero the Image Digitizer or A/D converter at the appropriate time.
Distinguishing Features
* Programmable 12-bit Video Timing * Bidirectional HSYNC and CLOCK Pins * Horizontal Sync Noise Gating * External VCO Support * Standard MPU Interface * TTL Compatible * + 5 V Monolithic CMOS * 28-pin PLCC Package * Typical Power Dissipation: 300mW
Applications
* * * * Image Processing Video Digitizing Desktop Publishing Graphic Art Systems
Functional Block Diagram
Noise-Gated CSYNC* HSYNC OSC1 OSC1* OSC2 OSC2* M U X XTAL OSC to Pixel Clock Generator
Phase Comparator
PCOUT
CLOCK 3-State Buffer Horizontal Counter
Horizontal VIDEO SYNC Detect SYNC Noise Gate Video Timing Control
ZERO CLAMP HSYNC
CAPTURE Vertical SYNC Processor
VSYNC* FIELD
CSYNC*
D0-D7
RD*
WR*
A0
Brooktree
(R)
Brooktree Division * Rockwell Semiconductor Systems, Inc. * 9868 Scranton Road * San Diego, CA 92121-3707 619-452-7580 * 1-800-2-BT-APPS * FAX: 619-452-1249 * Internet: apps@brooktree.com * L261_H
Ordering Information
Model Number BT261KPJ Package 28-pin Plastic J-lead Ambient Temperature Range 0 to +70C
Copyright (c) 1997 Brooktree Corporation. All rights reserved. Print date: September 1993 Brooktree reserves the right to make changes to its products or specifications to improve performance, reliability, or manufacturability. Information furnished by Brooktree Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Brooktree Corporation for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by its implication or otherwise under any patent or patent rights of Brooktree Corporation. Brooktree products are not designed or intended for use in life support appliances, devices, or systems where malfunction of a Brooktree product can reasonably be expected to result in personal injury or death. Brooktree customers using or selling Brooktree products for use in such applications do so at their own risk and agree to fully indemnify Brooktree for any damages resulting from such improper use or sale. Brooktree is a registered trademark of Brooktree Corporation. Product names or services listed in this publication are for identification purposes only, and may be trademarks or registered trademarks of their respective companies. All other marks mentioned herein are the property of their respective holders. Specifications are subject to change without notice.
PRINTED IN THE UNITED STATES OF AMERICA
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
TABLE OF CONTENTS
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
MPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Video Input / Sync Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Horizontal Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Horizontal Sync Separation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 HSYNC Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 VSYNC* Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 FIELD Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 CLAMP and ZERO Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Capture Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 External VCO Pixel Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Phase/Frequency Detector Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Two Forms of Noise Gating Available . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 The Status Registers SR00 and SR05 Used in Automatic Phase Limiting . . . . . . . 15 Asynchronous (Unlocked) Pixel Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Horizontal Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Command Register_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Command Register_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Command Register_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Command Register_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 VSYNC Sample Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 OSC Count Low and High Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 HSYNC Start and Stop Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 CLAMP Start and Stop Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 ZERO Start and Stop Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 FIELD Gate Start and Stop Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Noise Gate Start and Stop Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Brooktree
(R)
L261_H
iii
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
HCOUNT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Phase Locking With the 74HC4046 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Interfacing to the Bt218 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Interfacing to the Bt252 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Interfacing to the Bt254 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 ESD and Latchup Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Parametric Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DC Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 AC Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Brooktree
(R)
L261_H
iv
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
Brooktree
(R)
L261_H
v
BT261
LIST OF FIGURES
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
List of Figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Operation of FIELD and CAPTURE Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 External VCO Configuration.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 (a) Actual Gate-Level Implementation of Phase Limiting and Noise Gating (b,c, and d) Minimized Block Diagrams Corresponding to Waveforms in Figure 5 12 Phase-Comparator State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Examples of Phase Comparator Operation With Different Types of Error and Different Implementations of Phase Limiting and Noise Gating 14 PLL Performance Can Be Monitored Using SR05 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Pixel Clock Output Timing When Generated From Higher Speed Oscillator . . . . . . . . . . 17 BT261 Pinout Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 BT261 Suggested Register Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Operation of the BT261 with the 74HC4046A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Interfacing the Bt218. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Interfacing to the Bt252 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Interfacing to the Bt254. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
v
L261_H
Brooktree
(R)
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
LIST OF TABLES
List of Tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Internal Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Descriptions Grouped By Pin Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 BT261 Suggested Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Operation on the BT261 with the 74HC4046A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 BT261 Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Brooktree
(R)
L261_H
vi
BT261
LIST OF TABLES
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
vii
L261_H
Brooktree
(R)
CIRCUIT DESCRIPTION
MPU Interface
As seen in the functional block diagram, the BT261 supports an MPU interface via (D0-D7, RD*, WR*, and A0). MPU operations are asynchronous to the clocks. Refer to the Timing Waveforms section for further information. A0 is used to select either the internal 5-bit address register (A0 = logical zero) or the control register specified by the address register (A0 = logical one). ADDR5-ADDR7 are ignored during MPU write cycles, and are in an unknown state when read by the MPU. ADDR0 corresponds to D0 and is the least significant bit. ADDR0-ADDR4 increment following any MPU read or write cycle to a control register other than the address register. MPU write cycles to reserved addresses are ignored and MPU read cycles from reserved addresses return invalid data. Table 1 shows the internal register addressing.
Table 1. Internal Register Addressing ADDRO - ADDR4 $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C Addressed by MPU command register_0 command register_1 command register_2 command register_3 VSYNC sample register OSC count low register OSC count high register status register HSYNC start low register HSYNC start high register HSYNC stop low register HSYNC stop high register CLAMP start low register
Brooktree
(R)
L261_H
3
CIRCUIT DESCRIPTION
Video Input / Sync Detector
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
Table 1. Internal Register Addressing ADDRO - ADDR4 $0D $0E $0F $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A $1B $1C $1D $1E $1F Addressed by MPU CLAMP start high register CLAMP stop low register CLAMP stop high register ZERO start low register ZERO start high register ZERO stop low register ZERO stop high register FIELD gate start low register FIELD gate start high register FIELD gate stop low register FIELD gate stop high register noise gate start low register noise gate start high register noise gate stop low register noise gate stop high register HCOUNT low register HCOUNT high register reserved reserved
Video Input / Sync Detector
Either an AC-coupled video signal or a DC-coupled TTL-compatible composite sync signal may be input via the VIDEO input pin (negative-going sync polarity). When AC coupled, the clamping circuitry attempts to force the VIDEO pin voltage during sync tips to VCC/2. Command register_0 specifies the threshold above the sync tip to use for sync detection. If the sync tip on VIDEO is below the selected threshold, composite sync information is detected and output onto CSYNC* with no pipeline delay and asynchronous to the pixel clock. Typically, the VIDEO input will be connected to the TTL-compatible CSYNC* output of the Bt252/254 Image Digitizer, and the highest sync slicing level will be selected.
4
L261_H
Brooktree
(R)
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
CIRCUIT DESCRIPTION
Horizontal Counter
Horizontal Counter
The rising edge of pixel clock (CLOCK) increments a 12-bit horizontal counter used to generate horizontal video timing information. The value of the counter is compared to various registers to determine when signals are to be asserted (set high) and negated (set low). $000 corresponds to the falling edge of CSYNC*. When the part is used with an external high-speed oscillator and divided down to generate the pixel clock, there is no pipeline delay between CSYNC* and count zero. However, when the part is used in phase locked loop mode with an external VCO, there is a three-pixel-clock pipeline delay between CSYNC* and count zero.
Horizontal Sync Separation
The BT261 separates horizontal sync information from CSYNC* by use of the horizontal noise gate register, which derives gated composite sync by removing equalization and serration pulses at half-line intervals. Two 12-bit noise gate start and stop registers specify at what horizontal count (with pixel clock resolution) to respectively ignore or accept falling sync transitions on CSYNC*. The sync noise gating is provided to filter incorrect horizontal sync information from noisy video signals. The noise gating also serves a second purpose: to filter serration and equalization pulses at half-line intervals from CSYNC* during the vertical retrace interval. This enables steady synchronization of horizontal sync information during vertical retrace intervals.
HSYNC Input/Output
The HSYNC output may be programmed to be either active high or active low. The start value sets the rising edge and the stop value sets the falling edge of HSYNC relative to count zero of the horizontal counter. The beginning or falling edge of HSYNC is typically programmed to be coincident with the beginning of the noise-gated CSYNC*. The HSYNC output may be three-stated via the command register. HSYNC may also be configured as an input, enabling external circuitry to generate HSYNC and drive the phase comparator.
Brooktree
(R)
L261_H
5
CIRCUIT DESCRIPTION
VSYNC* Output
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
VSYNC* Output
The VSYNC register defines the clock count from the falling edge of nongated CSYNC* at which point CSYNC* is sampled to determine if the video signal is in the vertical interval. Since nongated CSYNC is used to start the VSYNC counter, two samples per horizontal line are taken during the vertical interval because of equalization and serration pulses. For each scan line that the sample is a logical zero, the VSYNC* output is a logical zero. Thus, the VSYNC sample register should be programmed so that the sample occurs well after the end of CSYNC* and before subsequent equalization/serration pulses. VSYNC is output on the rising edge of PCLK.
FIELD Output
The FIELD output is derived from the vertical sync information. By positioning the FIELD gate start/stop values a half-line interval apart, the half-line delay in vertical sync during the second field's vertical interval can provide a signal to distinguish the fields. The FIELD output is clocked by VSYNC*. Therefore, FIELD start and stop values should not coincide with VSYNC or VSYNC + HCOUNT/2. The FIELD GATE start and stop values define the clock count, from the beginning of the horizontal counter, at which to set the input to a register high (start value) or low (stop value). This register is clocked by VSYNC, which occurs half a line later in the transition from field 1 to field 2. The FIELD start and stop values must be separated by, approximately, HCOUNT/2, so that opposite states are reported on subsequent fields. The polarity is such that, with the FIELD GATE start value programmed less than the stop value, FIELD output is toggled high to indicate the beginning of field 1 and toggled low to indicate the beginning of field 2. The polarity of the FIELD pin may be inverted by swapping the start and stop register values. Figure 1 illustrates the operation of the FIELD gate and FIELD output.
6
L261_H
Brooktree
(R)
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
CIRCUIT DESCRIPTION
FIELD Output
Figure 1. Operation of FIELD and CAPTURE Outputs
Brooktree
(R)
L261_H
7
CIRCUIT DESCRIPTION
CLAMP and ZERO Outputs
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
CLAMP and ZERO Outputs
The CLAMP and ZERO outputs are provided to control the clamping and zero timing of the A/D converter or Image Digitizer. The start and stop timing is programmable by the MPU (in pixel clock cycles). ZERO is used to autocalibrate the comparators of the A/D converter or Image Digitizer. CLAMP is used to DC-restore the video signal. Both CLAMP and ZERO may be programmed to be either active high or active low.
Capture Output
The BT261 outputs a CAPTURE signal, which is a command register bit (CR05) synchronized to the vertical sync or FIELD signals. To capture a single frame of video in an interlaced system, the MPU resets the capture bit (CR5) low, then sets it high before the next rising edge of field. At the rising edge of FIELD, the CAPTURE output will be set to a logical zero until the next rising edge of FIELD (one frame time), when the CAPTURE output is set high. In a non-interlaced system, the MPU resets the capture bit (CR5) low, then sets it high before the falling edge of VSYNC*. When the falling edge of VSYNC* occurs, the capture output will be set high until the next falling edge of VSYNC*.
8
L261_H
Brooktree
(R)
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
CIRCUIT DESCRIPTION
External VCO Pixel Clock Generation
External VCO Pixel Clock Generation
An external VCO or pixel clock may be used to drive the BT261, as shown in Figure 2. The pixel clock signal (from the VCO if one is used) is connected to any one of the OSC input pins (the one used must be selected by command bits CR00-CR02). When the clock pin is configured as an input, it must also be driven by the pixel clock signal. The VCO must have positive control voltage (positive voltage forces a higher frequency). An on-chip phase comparator is available to compare the phase of HSYNC and the falling edge of the noise-gated CSYNC*. If the falling edge of the noise-gated CSYNC* occurs before the falling edge of HSYNC, the phase comparator "dumps" a charge onto an external capacitor, increasing the VCO frequency. If the falling edge of noise-gated CSYNC* occurs after the falling edge of HSYNC, the phase comparator "sinks" a charge from the external capacitor, decreasing the VCO frequency. Because of the internal delay elements, the phase comparison occurs approximately 500 ns after the falling edge of CSYNC*. The output of the phase comparator is PCOUT and it is a TTL-compatible three-statable output, which assumes a high-impedance state outside the phase-comparison window. The width of the output pulse on PCOUT is equal to the phase difference with a gain of 4/VCC. The "divide-by-N" for the PLL loop is the 12-bit HCOUNT register. Command register bits CR07 and CR06 must be set to (1,0) for proper operation. This configures the horizontal counter to be reset to zero upon reaching the HCOUNT value, which should be set to the number of pixels per line, minus 1.
Figure 2. External VCO Configuration.
HSYNC* lags CSYNC* Increase Frequency (PCOUT = 5V) No Change (PCOUT = High Impedance)
Second Order Loop Filter With Zero Included for Loop Stability R3 PCOUT R4 C2 C3 R5 BT261
HSYNC* leads CSYNC* Decrease Frequency (PCOUT = 0V)
Voltage Control 0-5V
VCO
OSC (N) CLOCK
Brooktree
(R)
L261_H
9
CIRCUIT DESCRIPTION
Phase/Frequency Detector Operation
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
Phase/Frequency Detector Operation
The phase comparator compares the phase of the falling edge of the noise-gated CSYNC* and generated HSYNC. The HSYNC can be either internally generated (and optionally output onto the HSYNC pin) or an external HSYNC signal can be input via the HSYNC pin.
Two Forms of Noise Gating Available
The BT261 offers two forms of noise gating to remove half-line serration and equalization pulses during the vertical interval, which can cause loop disturbances and wavering at the beginning of the displayed field. The first is a digital noise gate that is programmed in pixel clock events following the falling edge of composite sync. The noise-gate start must occur before the halfway point (HCOUNT/2). The noise-gate stop value must relate to a clock count a maximum distance from the end of line, defined as one half the minimum width of the serration pulse, less 500 ns. One half the equalization pulse provides the maximum error deviation for correct phase comparison. The 500 ns delay is required because of the offset used during phase limiting. Even when phase limiting is disabled, this delay is included in both the noise-gated CSYNC* and generated HSYNC* paths. Therefore, it must be accounted for in the noise-gate stop value (see Figure 3 [a-d]). The earliest possible noise-gate stop value permits the widest phase-error tracking range. For an acquisition range greater than one half the minimum equalization pulse width (2.3 s or 3.6 percent of nominal RS170A), the noise gate should be set transparent by programming a start value greater than HCOUNT and a stop value less than HCOUNT until lock is verified in the active field. The status registers can be monitored to verify lock.
10
L261_H
Brooktree
(R)
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
CIRCUIT DESCRIPTION
Two Forms of Noise Gating Available
A second analog noise gate is activated through the phase-limit feature. This function limits the duration of phase correction to about 500 ns per coincidence of noise-gated CSYNC* and generated HSYNC. The Phase Frequency Detector (PFD) makes its comparison about 500 ns after each falling transition of either HSYNC or CSYNC*. However, with phase limiting enabled, the comparison occurs only for a 500 ns interval while both signals are low. Thus, by limiting phase comparison to a 500 ns window, transitions at half-line intervals are not detected. The phase truncation that occurs when this feature is used limits the instantaneous phase-error impulse to about 500 ns that the loop can track. This may not be adequate for some video signal sources, such as heterodyne VCRs (without time-base correction) or electronic still photography (e.g., floppy disk) cameras. If the BT261 is programmed to permanently phase limit (CR22 set low), the phase-comparison duty is only ~0.8 percent and loop settling time is prolonged dramatically. Figure 3, Figure 4, and Figure 5 are block diagrams and examples demonstrating noise gating and phase limiting. Both forms of noise gate can be used together for maximum acquisition range with phase-error impulse tracking up to ~3.6 percent of the line rate (the maximum depends upon the minimum width of serration pulses). For an acquisition range that exceeds 2.3 s, the digital noise gate must be set transparent by temporarily setting noise-gate start value greater than HCOUNT with a stop value less than HCOUNT. Acquisition can then be automatic and the phase-limit feature (CR10 = CR22 = 1) can be used with phase-lock pixel count (CR27-CR24) programmed for less than 500 ns and the phase-lock line count (CR37-CR30) programmed for less than the field line count, minus the closed-loop settling time. When phase lock is verified (by strobing CR10 low and reading back SR0 = 1 or monitoring SR05), the digital noise-gate can be reactivated by restoring the noise-gate start value to less than HCOUNT/2. When the digital noise gate is active, the phase-limit feature should be disabled for maximum phase-error tracking range (determined by the phase-lock loop's closed-loop impulse response, but limited by one-half minimum serration pulse or noise-gate width). If instantaneous phase errors exceed phase-lock pixel count, the status register SR00 bit is forced to zero, even though the loop may be tracking the phase-error impulses. Since large phase errors usually occur in the vertical blanking interval, it is prudent to reset and monitor the lock status bit after the phase-lock line count has expired in the active field. A consistent zero in SR00 would dictate restarting the acquisition sequence outlined above to maintain phase lock. Similarly, SR05 may be monitored to determine locking status.
Brooktree
(R)
L261_H
11
CIRCUIT DESCRIPTION
Two Forms of Noise Gating Available
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
Figure 3. (a) Actual Gate-Level Implementation of Phase Limiting and Noise Gating (b,c, and d) Minimized Block Diagrams Corresponding to Waveforms in Figure 5
12
L261_H
Brooktree
(R)
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
CIRCUIT DESCRIPTION
Two Forms of Noise Gating Available
Figure 4. Phase-Comparator State Diagram
Brooktree
(R)
L261_H
13
CIRCUIT DESCRIPTION
Two Forms of Noise Gating Available
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
Figure 5. Examples of Phase Comparator Operation With Different Types of Error and Different Implementations of Phase Limiting and Noise Gating
14
L261_H
Brooktree
(R)
BT261
CIRCUIT DESCRIPTION
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock ControllerThe Status Registers SR00 and SR05 Used in Automatic Phase
The Status Registers SR00 and SR05 Used in Automatic Phase Limiting
Bits 0 and 5 of the status register can be used to debug phase-locked-loop operation of the BT261. Phase-lock pixel-count bits CR27-CR24 define a pixel count used by the BT261 to determine if the part is in "Lock." The BT261 compares the time during which the phase comparator is active (the PLL correction time) with the time defined in pixel count. If the compare time is less than phase-lock pixel count, the loop is considered locked and SR00 is not altered. If the compare time is greater than the phase-lock pixel count, SR00 is reset to zero. Previous to query, SR00 must be set to one by writing to command bit CR12. CR37-CR30 contains the phase-lock line count. This register determines the number of lines that must have a phase error less than that defined in the CR27-CR24 phase-lock pixel count for the system to be considered continuously locked. SR05 is reset to zero if there have been phase-lock line-count number of continuous lines with phase error less than that defined in the phase-lock pixel count. SR05 cannot be altered by the MPU. SR05 is set to one if SR00 is set to zero on any line (indicating a phase error greater than that defined in phase-lock pixel count). Bit 5 of the status register is used by the phase-limiting circuitry to determine if phase limiting should be enabled or disabled. If phase limiting is automatic, i.e., when phase limiting is enabled and lock is not overridden, (CR10 = CR22 = 1), SR05 determines whether phase limiting should be performed. SR05 is the lock control indicated in Figure 3a. The active period compared with the value in CR27-CR24 is output directly from the phase comparator. Because of this, all digital noise-gate and phase-limit operation is included when the phase error is compared with the phase-lock pixel-count value. Therefore, the value in CR27-CR24 must be less than 500 ns in the typical case or 350 ns in the worst case commercial temperature range. This requirement ensures that a phase-limited line is not incorrectly interpreted as a locked line. SR05 can be used as a PLL debug tool. If the status register is addressed and the RD* pin of the BT261 is held low, then SR05 will indicate the lock status. This bit will set low when lock is held for the number of lines defined in the phase-lock line count. When this condition is observed while the phase-comparator output is viewed through two vertical intervals, the BT261 response relative to the loop performance can be studied. Lock should be indicated well before the next vertical interval (see Figure 6). Phase-limit enable must be deactivated during this evaluation (CR10 = 0); otherwise, phase limiting will affect the ability to monitor the loop-acquisition time.
Brooktree
(R)
L261_H
15
CIRCUIT DESCRIPTION
Asynchronous (Unlocked) Pixel Clock Generation
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
Figure 6. PLL Performance Can Be Monitored Using SR05
Asynchronous (Unlocked) Pixel Clock Generation
Four oscillator clock inputs are provided (OSC), selectable by the MPU, configurable as either TTL or differential ECL inputs (designed to be driven by 10KH ECL using a single +5 V supply). The selected OSC input is divided down to the desired pixel clock rate and duty cycle. The pixel clock low and high times are programmable by the MPU (as a function of OSC clock cycles) via the OSC count low and high registers. Note that both the rising and falling edge of the OSC inputs are used when specifying the OSC count (for example, values of 2 for the OSC count low and high registers will divide the OSC clock symmetrically by two). The generated pixel clock is synchronized to the falling edge of the noise-gated CSYNC* each scan line. Each time a horizontal sync is detected on the VIDEO input, the CLOCK output is resynchronized by the OSC clock so that the beginning of a pixel clock cycle and the falling edge of the noise-gated CSYNC* are coincident (see Figure 7) within one half the period of the OSC input. While there is some sampling jitter on CLOCK associated with the falling edge of CSYNC*, the residual jitter in the remaining line interval is strictly a function of the OSC clock source jitter, symmetry, and amplitude/slew rate jitter, at the OSC input. Differential OSC signals of fast edges will minimize the latter contribution. There are three ways of controlling the horizontal counter, as determined by command bit CR07 and CR06. CR07 and CR06 are (0,1): if a falling edge of the noise-gated CSYNC* does not occur before the number of pixel clock cycles specified by HCOUNT, the horizontal counter stops at the HCOUNT value and is held there until the next falling edge of the noise-gated CSYNC*, at which time it is reset to zero. CLOCK stops in the high state at the HCOUNT value, until the next falling edge of the noise-gated CSYNC*.
16
L261_H
Brooktree
(R)
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
CIRCUIT DESCRIPTION
Asynchronous (Unlocked) Pixel Clock Generation
If a falling edge of the noise-gated CSYNC* occurs before the number of pixel clock cycles specified by HCOUNT, the horizontal counter is reset to zero by the falling edge of the noise-gated CSYNC*. CLOCK will be continuous and is resynchronized to each falling edge of the noise-gated CSYNC*. This mode is used if the number of pixel clock cycles per scan line is known and is a fixed number. CR07 and CR06 are (1,1): if a falling edge of the noise-gated CSYNC* does not occur before the number of pixel clock cycles specified by HCOUNT, the horizontal counter is reset to zero upon reaching HCOUNT, and begins incrementing again, until the next falling edge of the noise-gated CSYNC* or HCOUNT value is reached. CLOCK is continuous and is resynchronized to each falling edge of the noise-gated CSYNC*. If a falling edge of the noise-gated CSYNC* occurs before the number of pixel clock cycles specified by HCOUNT, the horizontal counter is cleared at the falling edge of the noise-gated CSYNC*, and begins incrementing again, until the next falling edge of the noise-gated CSYNC* or HCOUNT value is reached. CLOCK will be continuous and is resynchronized to the falling edge of the noise-gated CSYNC*. This mode is used if the number of pixel clock cycles per scan line is not known or an arbitrary value is to be used. CR07 and CR06 are (1,0): Resets H counter at HCOUNT only.
Figure 7. Pixel Clock Output Timing When Generated From Higher Speed Oscillator
Noise-Gated CSYNC
Clock HCOUNT Detail HCOUNT
Noise-Gated CSYNC
OSC Count Clock Low
OSC Count High
Clock Cycle Restarted
OSC
Brooktree
(R)
L261_H
17
CIRCUIT DESCRIPTION
Pin Descriptions
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
Pin Descriptions
Table 2. Pin Descriptions Grouped By Pin Function Pin Name HSYNC Description Horizontal sync input/output (TTL compatible). As an output, HSYNC is programmed to be either a logical zero or logical one during the desired horizontal sync interval. It is output following the rising edge of CLOCK. As an input, it is input into the phase comparator asynchronously to the clocks with no pipeline delays. Vertical sync output (TTL compatible) with a negative composite sync output. VSYNC* is a logical zero for scan lines during detected vertical sync intervals on the VIDEO input. It is output following the rising edge of CLOCK. Composite sync output (TTL compatible). CSYNC* is a logical zero during negative composite sync intervals detected on the VIDEO input. It is output asynchronous to the clocks with no pipeline delays. Zero output (TTL compatible). This output is used to control the ZERO input of the image digitizer or A/D converter. It may be programmed to be either active high or active low and is output following the rising edge of CLOCK. Clamp output (TTL compatible). This output is used to control the CLAMP input of the image digitizer or A/D converter. It may be programmed to be either active high or active low and is output following the rising edge of CLOCK. Even/odd field output (TTL compatible). For interlaced operation, this output (with transitions coincident with the VSYNC* output) indicates whether the current field is even or odd; the polarity is programmable. For noninterlaced operation, this output is always either a logical one or a logical zero, depending on whether it is programmed to be active high or low. It is output on the falling edge of VSYNC*. Phase comparator output (TTL compatible). This three-state output indicates the phase difference in time between the generated horizontal sync signal (either the internally generated HSYNC or the HSYNC pin) and the recovered horizontal sync signal. High = lags, Low = leads. Video and composite sync input. Either a DC-coupled TTL composite sync information or an AC-coupled analog video signal (less than 2 V peak-to-peak) may be input via this pin for detection of sync information. Sync information must be of negative polarity. Pixel clock input/output (TTL compatible). The device may either drive this pin with a generated clock or an external pixel clock may drive this pin. When the CLOCK pin is externally driven, the selected OSC pin must also be driven. External clock inputs (TTL or ECL compatible). These inputs are programmed to be either TTL or ECL compatible (10KH differential ECL driven by a single +5 V supply). Active video output (TTL compatible). This output is active high for a frame duration and is synchronized to the vertical sync interval and FIELD signal. It is output following the rising edge of FIELD for interlaced, or the falling edge of VSYNC* if non-interlaced. Read control input (TTL compatible). If RD* is a logical zero, data is output onto D0-D7. RD* and WR* should not be asserted simultaneously.
VSYNC*
CSYNC*
ZERO
CLAMP
FIELD
PCOUT
VIDEO
CLOCK
OSC1, OSC1*, OSC2, OSC2* CAPTURE
RD*
18
L261_H
Brooktree
(R)
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
CIRCUIT DESCRIPTION
Pin Descriptions
Table 2. Pin Descriptions Grouped By Pin Function Pin Name WR* Description Write control input (TTL compatible). If WR* is a logical zero, data is written into the device via D0-D7. Data is latched on the rising edge of WR*. RD* and WR* should not be asserted simultaneously. Bidirectional data bus (TTL compatible). MPU data is transferred into and out of the device over this 8-bit data bus. If RD* is a logical one, D0-D7 are three-stated. Address control inputs (TTL compatible). A0 specifies whether the MPU is accessing the address register (A0 = 0) or the control register specified by the address register (A0 = 1). Power. Ground.
D0-D7 AO VCC GND
Figure 8. BT261 Pinout Diagram
PCOUT
CLOCK
25
24
23
22
21
20
19
OSC2*
OSC2
GND
VCC
N/C
D0 D1 D2 D3 D4 D5 D6
26 27 28 1 2 3 4
10 D7 5 11 6 7 8 9
18 17 16 15 14 13 12
OSC1 OSC1* VSYNC* FIELD CAPTURE CSYNC* VIDEO
RD*
WR*
A0
CLAMP
ZERO
Brooktree
HSYNC
(R)
L261_H
19
CIRCUIT DESCRIPTION
Pin Descriptions
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
20
L261_H
Brooktree
(R)
INTERNAL REGISTERS
Horizontal Counter
The 12-bit horizontal counter is incremented on the rising edge of CLOCK. It is not accessible by the MPU.
Command Register_0
This command register may be written to or read by the MPU at any time and is not initialized. CR00 corresponds to D0 and is the least significant bit.
CR07, CR06 Horizontal counter control (00) (01) (10) (11) reserved reset each noise-gated CSYNC* reset to zero upon reaching HCOUNT use both modes (01) and (10) A value of (01) forces the horizontal counter to be reset to zero at the beginning of every noise-gated CSYNC*. These modes should be selected when using a high-speed oscillator to divide down and generate the pixel clock. A value of (10) specifies that the horizontal counter will be reset to zero upon reaching the HCOUNT value. This mode should be selected when using the horizontal counter as a simple divide-by-N circuit (such as when using an external VCO in a traditional phase-locked loop application). Mode 11 can be used to correct for missing sync pulses on the input video. This bit is synchronized to VSYNC* and FIELD and output onto the CAPTURE output pin. These bits specify how much above the sync tip to slice VIDEO for sync detection. If inputting TTL sync information, the highest slicing level should be selected.
CR05 CR04, CR03
Capture strobe Sync detect select (00) 25 mV (01) 50 mV (10) 100 mV (11) 125 mV Clock input select (000) TTL compatible OSC1 (001) TTL compatible OSC1* (010) TTL compatible OSC2 (011) TTL compatible OSC2* (100) ECL compatible OSC1, OSC1* (101) ECL compatible OSC2, OSC2* (110) reserved (111) reserved
CR02-CR00
These bits specify which OSC input is to be used to generate pixel clock information. ECL input selection is compatible with 10KH differential ECL driven by a single +5 V supply.
Note:
When the clock pin is driven, the selected OSC pin(s) must also be driven.
Brooktree
(R)
L261_H
21
INTERNAL REGISTERS
Command Register_1
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
Command Register_1
This command register may be written to or read by the MPU at any time and is not initialized. CR10 corresponds to D0 and is the least significant bit.
CR17 Interlaced or noninterlaced select (0) (1) CR16 noninterlaced operation interlaced operation This bit specifies whether an interlaced or noninterlaced video signal is being digitized. The MPU must write a logical zero followed by a logical one to this bit to reset the status bit (SR00) to a logical one. This bit specifies whether the CLOCK pin is three-stated (logical one) or is actively driven (logical zero). A logical one enables an external pixel clock to drive the internal counters.
CLOCK output disable (0) (1) drive CLOCK output three-state CLOCK output
CR15
CSYNC* output disable (0) (1) drive CSYNC* output three-state CSYNC* output
This bit specifies whether the CSYNC* output is three-stated (logical one) or is actively driven (logical zero).
CR14
VSYNC* output disable (0) (1) drive VSYNC* output three-state VSYNC* output
This bit specifies whether the VSYNC* output is three-stated (logical one) or is actively driven (logical zero).
CR13
HSYNC output disable (0) (1) drive HSYNC output three-state HSYNC output
This bit specifies whether the HSYNC output is three-stated (logical one) or is actively driven with the internally generated HSYNC signal (logical zero). If external circuitry is driving the HSYNC pin, this bit must be set to a logical one.
CR12
Reset lock loss status bit (0) (1) set status bit SR00 inactive
This bit sets SR00, which is used to indicate loss of lock. The MPU must write a logical zero to this bit to restart the process.
CR11
Phase comparator input select (0) (1) HSYNC pin internally generated HSYNC
One input to the phase comparator is recovered composite sync. The other input to the phase comparator is specified by this bit to be either the internally generated HSYNC or the HSYNC pin. When an external source is driving the HSYNC pin, this bit should be set to a logical zero. If this bit is a logical one, both horizontal sync signals (recovered and either internally or externally generated) must be present to adjust the VCO frequency. If one is missing, the VCO frequency is not adjusted. If this bit is a logical zero, a missing horizontal sync signal will adjust the VCO frequency.
CR10
Phase limit enable (0) (1) inhibit phase limiting enable phase limiting
22
L261_H
Brooktree
(R)
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
INTERNAL REGISTERS
Command Register_2
Command Register_2
This command register may be written to or read by the MPU at any time and is not initialized. CR20 corresponds to D0 and is the least significant bit. CR27, CR24 Phase lock pixel count (0001) 2 clock cycles (1111) 16 clock cycles These bits specify the maximum number of pixel clock cycles between the falling edge of noise-gated CSYNC* and the HSYNC signal (either internally or externally generated) to be considered locked. If the number of pixel clock cycles between the falling edge of noise-gated CSYNC* and the HSYNC signal exceed this value, lock is considered to be lost for that scan line, and the lock loss status bit (SR00) is set to a logical zero. If this bit is a logical one, the CLOCK output is stopped in the logical one state when the horizontal counter reaches the HCOUNT value. This ensures a minimum pulse width when the noise-gated CSYNC* signal is asynchronously sampled. If it is a logical zero, the CLOCK output will continuously clock (if command bit CR16 is a logical zero). This bit is ignored if an external pixel clock is driving the CLOCK pin (command bit CR16 is a logical one). If the BT261 goes out of lock, the phase limiter is automatically disabled until it is back in lock. If this bit is a logical zero, this function is overridden.
CR23
Pixel clock mask enable (0) (1) continuous pixel clock stop pixel clock at HCOUNT
CR22
Lock override (1) (0) normal operation tell phase comparator it's locked
CR21, CR20
Pixel clock select (00) (01) (10) (11) OSC inputs external pixel clock OSC drives CLOCK direct reserved
These bits specify whether to use the OSC-generated pixel clock or an external pixel clock (driving the CLOCK pin) to clock internal counters. In mode (00), the selected OSC input(s) is divided down by the OSC count registers to generate the pixel clock (CLOCK). If mode (01) is selected, an external pixel clock must drive the CLOCK pin and one of the OSC inputs. Command bit CR16 must be a logical one. If mode (10) is selected, the OSC clock is output directly onto the CLOCK pin. The OSC count low and high registers are ignored.
Brooktree
(R)
L261_H
23
INTERNAL REGISTERS
Command Register_3
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
Command Register_3
This command register may be written to or read by the MPU at any time and is not initialized. CR30 corresponds to D0 and is the least significant bit.
CR37, CR30
Phase lock line count (0000 0000) (0000 0001) (1111 1111) 1 scan line 2 scan lines 256 scan lines
These bits specify the number of consecutive scan lines for which lock must be maintained. If lock is not maintained for the specified number of scan lines, the phase limiter is disabled only if command bit CR22 is a logical one. SR05 is set to zero if lock is maintained for the specified number of scan lines.
VSYNC Sample Register
This 8-bit register specifies the number of pixel clock cycles after the falling edge of nongated CSYNC* at which to sample the CSYNC* signal each scan line. By doing this, two samples per line will be taken during the vertical interval when half-line pulses are present. The FIELD gate is programmed with the horizontal counter values (which use only noise-gated CSYNC*); when sampling of the input sync occurs, VSYNC will toggle one half-line earlier at the beginning of field two as opposed to the beginning of field one. This register may be written to or read by the MPU at any time and is not initialized. Values from $00 (1) to $FF (256) may be specified. A value of 1/8 HCOUNT is recommended (~8 s for the 15.75 KHz line-rate video). This is different from the 1/4 and 3/4 HCOUNT required for FIELD-gate start and stop values, and greater than the 5 s maximum width of sync pulses. For a conventional video input with negative-going syncs, this produces a negative-going VSYNC* at the number of clock cycles specified after the falling CSYNC* edge. There is a 3-pixel-clock pipeline delay in clearing the horizontal counter when the part is used in phase-lock loop mode. When the pixel clock is generated by dividing down an external oscillator, this delay is in oscillator clocks. Thus, the output of this signal with respect to CSYNC* may be delayed (see Figure 8).
OSC Count Low and High Registers
These two 4-bit registers specify the number of rising and falling edges of an OSC input the pixel clock output (CLOCK) is to be low and high. Values from $02 (2) to $OE (15) may be specified. These registers may be written to or read by the MPU at any time and are not initialized. A value of $00 results in no pixel clock generation while the OSC inputs are used. The counters clock on both the rising and falling edge of the selected OSC input. For example, values of 4, 4 in OSC count low and high would result in a pixel clock with one fourth the frequency of the oscillator.
24
L261_H
Brooktree
(R)
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
INTERNAL REGISTERS
Status Register
Status Register
This status register may be read by the MPU at any time and is not initialized. MPU write cycles to this register are ignored. SR00 corresponds to D0 and is the least significant bit.
SR00
Lock-loss status (pixel count related) (0) (1) lock loss detected reset or no lock loss
This bit reset if loss of lock is indicated. "Loss of lock" is defined as a greater phase error between noise-gated CSYNC* and generated HSYNC* than the phase-lock pixel count (CR27-CR24). It is reset by writing to command bit CR12. This bit is set if one line of video has a phase error between generated HSYNC and noise-gated CSYNC* greater than that defined by the phase-lock pixel count (CR24-CR27). This bit is reset if there have been phase-lock line count (CR37-CR30) consecutive lines with error less than that defined in the phase-lock pixel count.
SR05
Lock-loss bit (line-count related) (1) (0) lock loss detected lock detected for at least line-count number of lines
Brooktree
(R)
L261_H
25
INTERNAL REGISTERS
Status Register
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
Figure 9. BT261 Suggested Register Settings.
26
L261_H
Brooktree
(R)
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
INTERNAL REGISTERS
Status Register
Table 3. BT261 Suggested Register Settings Pixel Clock Rate NTSC(M) 12.2 MHz dec hex 63.556 s 779 30B 943 PAL (B, G, I) 14.75 MHz dec hex 64.0 s 3AF
Line Rate (HCOUNT) Number of pixels minus 1 (Noise Gate) Start 7 s Stop 61.76 s Start 4.7 s Stop 0 s Start 8.5 s Stop 9 s
88 758 59 0 107 113
58 2F6 3B 0 6B 71
104 917 70 0 126 134
68 395 46 0 7E 86
(HSYNC) Negative polarity, 4.7 s wide
(CLAMP) One may CLAMP on burst back porch or sync tip (ZERO)
Start 8.5 s Stop 8.75 s Start 15 s Stop 45 s 8 s
107 110 189 566 98
6B 6E BD 236 62
126 130 223 668 118
7E 82 DF 29C 76
(Field Gate)
(VSYNC) This gives FIELD = 0, 1 for field one and two, respectively
Brooktree
(R)
L261_H
27
INTERNAL REGISTERS
HSYNC Start and Stop Registers
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
HSYNC Start and Stop Registers
These two 16-bit registers specify the number of pixel clock cycles after the falling edge of noise-gated CSYNC* at which to assert or negate the HSYNC output. The [start value] specifies the number of CLOCK cycles after the falling edge of noise-gated CSYNC* that the HSYNC output is set high. The [stop value] specifies the number of CLOCK cycles after the falling edge of noise-gated CSYNC* that the HSYNC output is set low. If [start value] = [stop value], HSYNC will remain a constant logical one. Values from $0000 (1) to $0FFF (4096) may be specified. Note that there is a variable pipeline delay between the CSYNC* and HSYNC outputs. There is a 3-pixel-clock pipeline delay in clearing the horizontal counter when the part is used in phase-lock loop mode. When the pixel clock is generated by dividing down an external oscillator, this delay is in oscillator clocks. Thus, output of this signal with respect to CSYNC* may be delayed. D4-D7 of HSYNC start high are ignored during MPU write cycles and return a logical zero during MPU read cycles. The 16-bit HSYNC start register is not updated until the write cycle to the HSYNC start high register. Thus, the writing sequence should be [HSYNC start low] [HSYNC start high]. D4-D7 of HSYNC stop high are ignored during MPU write cycles and return a logical zero during MPU read cycles. The 16-bit HSYNC stop register is not updated until the write cycle to the HSYNC stop high register. Thus, the writing sequence should be [HSYNC stop low] [HSYNC stop high].
HSYNC Start/Stop High Data Bit Cascaded Value D3 H11 D2 H19 D1 H9 D0 H8 D7 H7 D6 H6 D5 H5 HSYNC Start/Stop Low D4 H4 D3 H3 D2 H2 D1 H1 D0 H0
28
L261_H
Brooktree
(R)
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
INTERNAL REGISTERS
CLAMP Start and Stop Registers
CLAMP Start and Stop Registers
These two 16-bit registers specify the horizontal count (in pixel clocks) at which to assert and negate the CLAMP output. The [start value] specifies the number of CLOCK cycles after the falling edge of noise-gated CSYNC* that CLAMP is set high. The [stop value] specifies the number of CLOCK cycles after the falling edge of noise-gated CSYNC* that CLAMP is set low. If [start value] = [stop value], CLAMP will remain a constant logical one. Values from $0000 (1) to $0FFF (4096) may be specified. There is a 3-pixel-clock pipeline delay in clearing the horizontal counter when the part is used in phase-lock loop mode. When the pixel clock is generated by dividing down an external oscillator, this delay is in oscillator clocks. Thus, output of this signal with respect to CSYNC* may be delayed. D4-D7 of CLAMP start high are ignored during MPU write cycles and return a logical zero during MPU read cycles. The 16-bit CLAMP start register is not updated until the write cycle to the CLAMP start high register. Thus, the writing sequence should be [clamp start low] [clamp start high]. D4-D7 of CLAMP stop high are ignored during MPU write cycles and return a logical zero during MPU read cycles. The 16-bit CLAMP stop register is not updated until the write cycle to the CLAMP stop high register. Thus, the writing sequence should be [clamp stop low] [clamp stop high].
CLAMP Start/Stop High Data Bit Cascaded Value D3 H11 D2 H19 D1 H9 D0 H8 D7 H7 D6 H6 CLAMP Start/Stop Low D5 H5 D4 H4 D3 H3 D2 H2 D1 H1 D0 H0
A value corresponding to 1 s after the falling edge of CSYNC* is recommended for the [start] value, and a value of 1 s before the rising edge of CSYNC* is recommended for the [stop] value if DC restoration is to occur during the horizontal sync interval. If DC restoration is to occur during the back porch interval, a value corresponding to 500 ns after the rising edge of CSYNC* is recommended for the [start] value and a value corresponding to 2.5 s after the rising edge of CSYNC* is recommended for the [stop] value. For restoration of signals with subcarrier-encoded NTSC or PAL, the 7.8-9.4 s interval (12-15 percent of HCOUNT) following the color burst may be better for clamping a luminance signal with residual burst.
Brooktree
(R)
L261_H
29
INTERNAL REGISTERS
CLAMP Start and Stop Registers
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
ZERO Start and Stop Registers
These two 16-bit registers specify the number of pixel clock cycles after the falling edge of noise-gated CSYNC* at which to assert or negate the ZERO output. The [start value] sets this output high at the specified number of CLOCK cycles following the falling edge of noise-gated CSYNC*. The [stop value] sets this output low at the specified number of CLOCK cycles following the falling edge of noise-gated CSYNC*. If [start value] = [stop value], ZERO will remain a constant logical one. Values from $0000 (1) to $0FFF (4096) may be specified. There is a 3-pixel-clock pipeline delay in clearing the horizontal counter when the part is used in phase-lock loop mode. When the pixel clock is generated by dividing down an external oscillator, this delay is in oscillator clocks. Thus, output of this signal with respect to CSYNC* may be delayed. D4-D7 of ZERO start high are ignored during MPU write cycles and return a logical zero during MPU read cycles. The 16-bit ZERO start register is not updated until the write cycle to the ZERO start high register. Thus, the writing sequence should be [zero start low] [zero start high]. D4-D7 of ZERO stop high are ignored during MPU write cycles and return a logical zero during MPU read cycles. The 16-bit ZERO stop register is not updated until the write cycle to the ZERO stop high register. Thus, the writing sequence should be [zero stop low] [zero stop high].
ZERO Start/Stop High Data Bit Cascaded Value D3 H11 D2 H19 D1 H9 D0 H8 D7 H7 D6 H6 D5 H5 ZERO Start/Stop Low D4 H4 D3 H3 D2 H2 D1 H1 D0 H0
Since an active high signal is need for the Bt218, Bt252, and Bt254 during non-acquisition intervals, the ZERO output can be programmed to be within the horizontal retrace interval. In addition, these devices produce a significant impulse on their video input following the zero pulse, which can affect clamping stability. So, the pulse is best positioned within the active CLAMP pulse to divert this energy. Both CLAMP and ZERO pins may be driven with the same timing.
30
L261_H
Brooktree
(R)
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
INTERNAL REGISTERS
FIELD Gate Start and Stop Registers
FIELD Gate Start and Stop Registers
These two 16-bit registers specify the number of pixel clock cycles after the falling edge of noise-gated CSYNC* at which to start and stop the FIELD gate "window." With the noise gate properly programmed to ignore half-line vertical interval pulses, the VSYNC* transition will occur half a line later during the vertical sync interval between fields one and two (assuming a typical 2:1 interlaced video signal). By programming the FIELD start and stop values to have an interval exceeding half a line (e.g. starting at 1/4 line time and stopping at 3/4 line time), the FIELD output is low during field one if [start value] < [stop value] or high during field one if [start value] > [stop value], with transitions at every falling edge of VSYNC*. If [start value] = [stop value], FIELD will remain a constant logical one. Values from $0000 (1) to $0FFF (4096) may be specified. Field edge coincides with VSYNC* falling edge. D4-D7 of FIELD gate start high are ignored during MPU write cycles and return a logical zero during MPU read cycles. The 16-bit FIELD gate start register is not updated until the write cycle to the FIELD gate start high register. Thus, the writing sequence should be [field gate start low] [field gate start high]. D4-D7 of FIELD gate stop high are ignored during MPU write cycles and return a logical zero during MPU read cycles. The 16-bit FIELD gate stop register is not updated until the write cycle to the FIELD gate stop high register. Thus, the writing sequence should be [field gate stop low] [field gate stop high].
FIELD Gate Start/Stop High Data Bit Cascaded Value D3 H11 D2 H19 D1 H9 D0 H8 D7 H7 D6 H6 FIELD Gate Start/Stop Low D5 H5 D4 H4 D3 H3 D2 H2 D1 H1 D0 H0
Values of one fourth HCOUNT and three fourths HCOUNT are recommended for start and stop values, resulting in an active high FIELD output (field one = 1, field two = 0).
Brooktree
(R)
L261_H
31
INTERNAL REGISTERS
Noise Gate Start and Stop Registers
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
Noise Gate Start and Stop Registers
These two 16-bit registers specify the number of pixel clock cycles after the falling edge of CSYNC* at which to force the noise gate to be closed (start value) or open (stop value). If [start value] = [stop value], the noise gate will remain closed. The noise-gate start value should be activated no later than HCOUNT/2. The noise-gate stop value should be within one half the minimum serration pulse width minus 500 ns to the end of the horizontal line. This gating is required because of the state counter that is used to determine the phase comparison output and the 500 ns delay that is used for phase limiting. Because of this stop-value limitation, the digital noise gate can be used to track phase errors no greater than one half the minimum serration pulse width. This translates into 2.3 s and 0.75 s (3.6 percent and 1.2 percent of the line rate) for RS170A and RS343, respectively. For example:
Video Source RS170A RS343A Note: 1/2 Minimum Serration Pulse 2.3 s 0,75 s 261 Gate Delay 0,5 s 0,5 s Minimum Stop Value From End of Line 1.8 s 0,25 s Minimum Noise-Gate Stop-Value Time 61,76 s 63.31 s
The Brooktree Applications Handbook and the RS343A and RS170A specifications contain minimum serration pulse widths.
For wideband acquisition, the noise gate should be disabled by programming the start value greater and the stop value less than the number of pixels per line. Values from $0000 (1) to $0FFF (4096) may be specified. This register should be initialized early to minimize indeterminate outputs during vertical retrace. This register must be properly programmed when the part is used in either phase-lock loop mode or when an external oscillator is resynchronized. D4-D7 of noise gate start high are ignored during MPU write cycles and return a logical zero during MPU read cycles. The 16-bit noise gate start register is not updated until the write cycle to the noise gate start high register. Thus, the writing sequence should be [noise gate start low] [noise gate start high]. D4-D7 of noise gate stop high are ignored during MPU write cycles and return a logical zero during MPU read cycles. The 16-bit noise gate stop register is not updated until the write cycle to the noise gate stop high register. Thus, the writing sequence should be [noise gate stop low] [noise gate stop high].
Noise Gate Start/Stop High Data Bit Cascaded Value D3 H11 D2 H19 D1 H9 D0 H8 D7 H7 D6 H6 Noise Gate Start/Stop Low D5 H5 D4 H4 D3 H3 D2 H2 D1 H1 D0 H0
32
L261_H
Brooktree
(R)
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
INTERNAL REGISTERS
HCOUNT Register
HCOUNT Register
This 12-bit register specifies the maximum number of pixel clocks to generate per horizontal line. In phase-locked applications, HCOUNT is the critical register that is resolution dependent. It should be programmed with the number of pixels per line required, minus 1. The other timing-dependent registers, including noise gate, ZERO, CLAMP, and HSYNC, will now all be programmed in terms of clock events, based upon the number of clocks per line defined in HCOUNT. For example, the HSYNC stop register is programmed to set output low at count zero, signifying the falling edge of HSYNC or the beginning of the line. The HSYNC start value is programmed to toggle high at 4.75 s into the horizontal line, signifying the beginning of the back porch, for RS170A. The HSYNC start value in terms of a 12.27 MHz clock (square pixels NTSC) would be 59 clocks, or ~4.7 s (see Figure 8). The HCOUNT low and high registers are cascaded to form a 12-bit HCOUNT register. D4-D7 of HCOUNT high are ignored during MPU write cycles and return a logical zero during MPU read cycles. The 12-bit HCOUNT register is not updated until the write cycle to the HCOUNT high register. Thus, the writing sequence should be [HCOUNT low] [HCOUNT high]. Values from $0000 (1) to $0FFF (4096) may be specified. This register should be written first during initialization to minimize indeterminate output activity.
HCOUNT High Data Bit Cascaded Value D3 H11 D2 H19 D1 H9 D0 H8 D7 H7 D6 H6 D5 H5 HCOUNT Low D4 H4 D3 H3 D2 H2 D1 H1 D0 H0
Brooktree
(R)
L261_H
33
INTERNAL REGISTERS
HCOUNT Register
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
34
L261_H
Brooktree
(R)
APPLICATION INFORMATION
Phase Locking With the 74HC4046
Applications that call for multiple resolutions with clock rates in the 9-18 MHz range may employ the circuit (Figure 10) shown with a 74HC4046 and a passive loop filter. Residual jitter can be less than 30 ns, which is subpixel but not as good as can be achieved with LC-tuned VCOs or VCXOs. These have narrower tuning ranges. The loop parameters were obtained from a design program provided for the 74HC4046 with the BT261's phase comparator emulating the type 2 phase detector with 4/VCC gain (Note 1). The type 1 second-order loop is designed for 10 dB ripple suppression in closed-loop response with a critically damped response and a tracking range of 4 percent, which is adequate for most stable sources (e.g., broadcast, camera, and videodisc). Nonstandard video sources (e.g., heterodyne VCRs or floppy disk ESP cameras) may require a prefilter PLL for adequate tracking. Third-order loop filters may yield faster loop response rolloff, which reduces jitter but can prolong loop settling time. The same circuit can be extended to 26 MHz for genlocking to higher raster frequency sources (such as noninterlaced VGA) or adapted to crystal-based operation up to 10 MHz. The VCO timing-capacitor value must be reduced to 40 pF for the former higher frequency case or replaced with a parallel resonant crystal in the latter case. Loop filter values will vary slightly in conjunction with modification of R1 and R2 VCO gain-setting resistors. In general, VCO capture range must be limited to one octave to prevent harmonic lockup. With the low-input bias current of the 74HC4046, passive filters are simpler than active filters and can better accommodate large-value polarized capacitors. Bipolar VC(X)O implementations that use the MC4024, 74LS624, or MN3106 require active buffers with bias currents less than 10 A to limit control voltage droop across the 64 s interval between phase-comparison pulses. Low-absorption Mylar or Teflon capacitors in the loop filter can minimize jitter caused by capacitance modulation.
Brooktree
(R)
L261_H
35
APPLICATION INFORMATION
Phase Locking With the 74HC4046
BT261
30MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
Figure 10. Operation of the BT261 with the 74HC4046A
Table 4. Operation on the BT261 with the 74HC4046A Tracking Range 9-18 MHz 17-26 MHz 200 ppm of crystal center frequency Oscillator Jitter <40 ns <40 ns <10 ns R1 R2 R3 R4 R5 C1 C2 C3 Wn Damping (3) 0.74 0.74 0.74
3.9 k 3.9 k 46 k
10 k 10 k 46 k
470 470 470
86 86 290
500 k 500 k 500 k
100 pF 40 pF 10 MHz Resonant Crystal
10 F 10 F 3.3 nF
1 F 1 F 300 pF
290 Hz 290 Hz 290 Hz
36
L261_H
Brooktree
(R)
BT261
30MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
APPLICATION INFORMATION
Interfacing to the Bt218
Interfacing to the Bt218
Figure 11 illustrates the interface of the BT261 to the Bt218 Flash A/D Converter. The VIDEO input of the BT261 connects to the VIN input of the Bt218 through a 1 F ceramic capacitor. The sync slicing level of the BT261 should be selected for optimum performance. The BT261 provides the ZERO and CLAMP signals required by the Bt218, in addition to the CLOCK. The HSYNC, VSYNC*, FIELD, and CAPTURE signals of the BT261 interface to the video timing controller and video DRAM controller.
Figure 11. Interfacing the Bt218
Brooktree
(R)
L261_H
37
APPLICATION INFORMATION
Interfacing to the Bt252
BT261
30MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
Interfacing to the Bt252
Figure 12 illustrates the interface of the BT261 to the Bt252 Image Digitizer. The VIDEO input of the BT261 connects directly to the CSYNC* output of the Bt252. As CSYNC* is a TTL-compatible output, the highest sync slicing level should be selected on the BT261. The BT261 provides the ZERO and CLAMP signals required by the Bt252, in addition to the CLOCK. The HSYNC, VSYNC*, FIELD, and CAPTURE signals of the BT261 interface to the video timing controller and video DRAM controller.
Figure 12. Interfacing to the Bt252
HSYNC VSYNC*
BT261
FIELD CAPTURE
To Video Timing Controller And DRAM Controller
VIDEO
ZERO CLAMP CLOCK
CSYNC* ZERO CLAMP CLOCK
Bt252
38
L261_H
Brooktree
(R)
BT261
30MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
APPLICATION INFORMATION
Interfacing to the Bt254
Interfacing to the Bt254
Figure 13 illustrates the interface of the BT261 to the Bt254 Image Digitizer. The VIDEO input of the BT261 connects directly to the CSYNC* output of the Bt254. As CSYNC* is a TTL-compatible output, the highest sync slicing level should be selected on the BT261. The BT261 provides the ZERO and CLAMP signals required by the Bt254, in addition to the (R,G,B) CLOCK inputs of the Bt254. The HSYNC, VSYNC*, FIELD, and CAPTURE signals of the BT261 interface to the video timing controller and video DRAM controller.
Figure 13. Interfacing to the Bt254
HSYNC VSYNC*
BT261
FIELD To Video Timing CAPTURE Controller And DRAM Controller
VIDEO
ZERO
CLAMP CLOCK
CSYNC*
ZERO
CLAMP RCLOCK GCLOCK
BCLOCK
Bt254
ESD and Latchup Considerations
Correct ESD-sensitive handling procedures are required to prevent device damage, which can produce symptoms of catastrophic failure or erratic device behavior with somewhat "leaky" inputs. Latchup can be prevented by ensuring that all VCC pins are at the same potential and that the VCC supply voltage is applied before the signal pin voltages. The correct power-up sequence ensures that any signal pin voltage will never exceed the power supply voltage by more than +0.5 V.
Brooktree
(R)
L261_H
39
APPLICATION INFORMATION
ESD and Latchup Considerations
BT261
30MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
40
L261_H
Brooktree
(R)
PARAMETRIC INFORMATION
DC Electrical Parameters
Table 5. Recommended Operating Conditions Parameter Power Supply Ambient Operating Temperature Video Input DC-coupled AC-coupled (1) Symbol VCC TA Min 4.75 0 0.2 Typ 5.00 Max 5.25 +70 5 2 Units V C V Vpp
Table 6. Absolute Maximum Ratings Parameter VCC (measured to GND) Voltage on any Signal Pin (1) Ambient Operating Temperature Storage Temperature Junction Temperature Vapor Phase Soldering (1 minute) GND-0.5 -55 -65 Symbol Min Typ Max 7.0 VCC + 0.5 Units V V
TA TS TJ TVSOL
+ 125 + 150 + 150 220
C C C C
Notes: (1). Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. This device employs high impedance CMOS devices on all signal pins. It should be handled as an ESD-sensitive device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V can induce destructive latchup.
Brooktree
(R)
L261_H
41
PARAMETRIC INFORMATION
DC Electrical Parameters
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
Table 7. DC Characteristics (1 of 2) Parameter TTL Digital Inputs Input High Voltage Input High Voltage (1) HSYNC Pin Input Low Voltage Input Low Voltage (1) RD* Pin Input High Current (Vin = 2.4 V) Input Low Current (Vin = 0.4 V) Input Low Current (Vin = 0.4 V) VIDEO Pin Input Capacitance (f = 1 MHz, Vin = 2.4 V) OSC Digital Inputs TTL Mode Input High Voltage (1) Input Low Voltage Input High Current (Vin = 2.4 V) Input Low Current (Vin = 0.4 V) Input Capacitance (f = 1 MHz, Vin = 2.4 V) ECL Mode Input High Voltage Input Low Voltage Input High Current (Vin = 4.0 V) Input Low Current (Vin = 0.4 V) Input Capacitance (f = 1 MHz, Vin = 2.4 V) Symbol Min Typ Max VCC + 0.5 VCC + 0.5 0.8 0.4 1 -1 -1.5 Units V V V V A A mA pF CIN 7 VCC + 0.5 0.8 1 -1 V V A A pF
VIH VIH VIL VIL IIH IIL IIL
2.0 2.2 GND-0.5
VIH VIL IIH IIL CIN
2.2 GND-0.5
7 VIH VIL IIH IIL CIN VCC-1.0 GND-0.5
VCC + 0.5 VCC-1.6 1 -1
V V A A pF
7
42
L261_H
Brooktree
(R)
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
PARAMETRIC INFORMATION
DC Electrical Parameters
Table 7. DC Characteristics (2 of 2) Parameter D0?-D7 Digital Outputs Output High Voltage (IOH = -400 A) Output Low Voltage (IOL = 6.4 mA) 3-state Current Output Capacitance Symbol Min Typ Max 0.4 VOH VOL IOZ COUT PCOUT Output Output High Voltage (IOH = -400 A) Output Low Voltage (IOL = 3.2 mA) 3-state Current Output Capacitance VOH VOL IOZ COUT Other Digital Outputs Output High Voltage (IOH = -400 A) Output Low Voltage (IOL = 3.2 mA) 3-State Current Output Capacitance VOH VOL IOZ COUT A pF 20 2.4 0.5 V A pF 20 0.4 V 2.4 400 V A pF 20 0.4 V 2.4 0.5 V Units V
Notes: (1). VIH, VIL for RD*, HSYNC, and OSC inputs are tested at 3 and 0 V but guaranteed by characterization. 2. Test conditions (unless otherwise specified):"Recommended Operating Conditions." Typical values are based on nominal temperature, i.e., room, and nominal voltage, i.e., 5 V.
Brooktree
(R)
L261_H
43
PARAMETRIC INFORMATION
AC Electrical Parameters
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
AC Electrical Parameters
Table 8. AC Characteristics Parameter OSC Cycle Time TTL mode ECL mode CLOCK Cycle Time (1) A0 Setup Time A0 Hold Time RD*/WR* Low Time RD*/WR* High Time RD* Asserted to Data Bus Driven RD* Asserted to Data Valid RD* Negated to Data Bus 3-Stated Write Data Setup Time Write Data Hold Time OSC High Time OSC Low Time OSC to CLOCK Output Delay VIDEO to CSYNC* Output Delay HSYNC, ZERO, CLAMP Output Delay VSYNC*, FIELD Output Delay PCOUT Output Delay Minimum Compare Differential VCC Supply Current ( 2) Symbol OSCmax 13.3 12.5 33.33 10 10 40 40 1 30 30 10 10 6 6 35 35 10 10 380 5 60 650 13 90 Min Typ Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Fmax 1 2 3 4 5 6 7 8 9 10 11 14 15 16 17 18 19 ICC
Notes: (1). Maximum load of 20 pf. (2). At Fmax. ICC (typ) at VCC = 5.0 V. ICC (max) at VCC = 5.25 V. OSC/PCLOCK = 2, CLOCK/HSYNC 100. 3. Test conditions (unless otherwise specified):"Recommended Operating Conditions." TTL input values are 0-3 V, with input rise/fall times 4 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. CLOCK, HSYNC, CLAMP, ZERO, VSYNC*, FIELD, CAPTURE, and CSYNC* output load 50 pF, D0-D7 output load 130 pF. Typical values are based on nominal temperature, i.e., room temperature, and nominal voltage, i.e., 5 V.
44
L261_H
Brooktree
(R)
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
PARAMETRIC INFORMATION
Timing Waveforms
Timing Waveforms
Figure 13. MPU Read/Write Timing
1
2
A0
Valid 3
RD*, WR* 6 5 D0-D7 (Read) 8 D0-D7 (Write) Data In (WR* = 0) Data Out (RD* = 0)
4
7
9
Brooktree
(R)
L261_H
45
PARAMETRIC INFORMATION
Timing Waveforms
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
Figure 14. Video/Output Timing
Figure 15. Video Input/Output Timing
HSYNC
19 VIDEO (HSYNC) 18 Below Specified Threshold 3-State
19
PCOUT
46
L261_H
Brooktree
(R)
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
PARAMETRIC INFORMATION
Timing Waveforms
Figure 16. Package Drawing--28-pin Plastic J-Lead (PLCC)
Unless otherwise specified: Notes: 1. Dimensions are in inches [millimeters]. 2. Tolerances are: .xxx 0.005 [0.127]. 3. PLCC packages are intended for surface mounting on solder lands on 0.050 [1.27] centers.
Brooktree
(R)
L261_H
47
PARAMETRIC INFORMATION
Revision History
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
Revision History
Table 9. BT261 Datasheet Revision History Revision G, H Date 09-16-93 Description In Table 1, HCOUNT start low/high register changed to HCOUNT low/high register. In the Internal Register Section, HCOUNT register changed from 16-bit to 12-bit. The Application Information Section was revised; 0.1 F ceramic capacitor changed to 1 F (this change applies to Figure 10 as well). Figures 1, 4, 5, 8 and 10 were revised.
48
L261_H
Brooktree
(R)
BT261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
PARAMETRIC INFORMATION
Revision History
Brooktree
(R)
L261_H
49
Brooktree
(R)
Brooktree Division Rockwell Semiconductor Systems, Inc. 9868 Scranton Road San Diego, CA 92121-3707 (619) 452-7580 1(800) 2-BT-APPS FAX: (619) 452-1249 Internet: apps@brooktree.com L261_H
printed on recycled paper

▲Up To Search▲

Price & Availability of BT261

	To Download BT261 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .